Manufacturing test involves testing complex circuits by applying stimulus and capturing responses in memory elements along with or without Built-In Self Tests (BIST) for memory cells. An important aspect of both these tests is response compaction in which the test response is compressed in both the space and time dimensions to a compact signature. Test response compaction schemes are typically based on XOR or multiple input signature register (MISR) schemes. MISR schemes, for example, can generate and store a resulting signature from test responses.
MISR has the advantage of having a memory and register, which can store the data of each cycle. By implementing the MISR, it is possible to make a comparison after all of the cycles have been scanned out. MISR poses several disadvantages, though. For example, with MISR schemes there can be poor diagnosability, faulty values which may be jumbled into the signature, as well as sequential and combinational overhead. In addition, there is low diagnostic resolution which does not allow for pinpointing the exact location of a failure; instead, it is only possible to identify a fault in the chip. Also, MISR schemes are not very scalable which leads to higher test time for a same number of scan outs.
On the other hand, by implementing the XOR schemes, it is possible to compare the signature of each cycle in order to isolate a failure and, hence have a higher diagnostic resolution. The XOR schemes also provide the following disadvantages: every cycle comparison leads to less efficient use of scan I/Os, aliasing effects occur when compression factor increases, also leading to higher test time because the number of signature comparison cycles will equal the length of scan segments. Also, XOR schemes are not scalable with respect to test time.